Low latency architecture design and implementation for short-time fourier transform algorithm on FPGA

摘要

This paper presents a low complex and low latency architecture to compute short-time Fourier transform (STFT). This new approach is based on reusing the calculations of the STFT at consecutive time instants. This leads to the significant saving in hardware with respect to fast Fourier transform based STFTs. In the proposed approach, an N/2-point FFT is computed, where N is the length of the window and is merged with the FFT of the previous N/2-point to generate an N-point FFT of the overlapped segment. As a result, the proposed STFT architecture presents an excellent trade-off in hardware utilization and latency. The proposed method needs to compute (S + 1) number of N/2-point FFTs instead of S number of N-point FFTs, where S is the number of overlapping segments.