Self-Assertive Generic UVM Testbench for Advanced Verification of Bridge IPs

摘要

This work focuses on the implementation of Universal Verification Methodology (UVM) on bridge protocols along with the conjunction of advanced verification environment. Bridge devices are helpful in joining two separate network device to establish a communication link in between them. This proposed testbench reusable environment is capable of verifying all bridge devices and improved result as compared to System Verilog testbench. As a case study, this paper takes ARM-Advanced High-Performance Bus (AHB) to Advanced eXtensible Interface (AXI4) Bridge v3.0 under consideration to prove the test results for bridge devices. The advanced verification testbench incorporates the illustrations regarding C.P.U timings, simulation timings, and functional coverage to check further improvement of Design functionality. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.