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Circuit Partitioning Problem Clustering Method Based on Adjacency Matrix Unification

机译:基于邻接矩阵统一的电路划分问题聚类方法

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The present work deals with artificial intelligence research. The problem of engineering software benchmarking study for the purpose of fitting for task type and computational resources is important today. This problem is often solved by the help of intelligence decision support systems (IDSS). Domain ontology is a typical knowledge representation model in such systems. Manual ontology development is a time-consuming and expensive process. Because of a great variety of circuit partitioning problem formulization, clustering is a necessary step of automated circuit partitioning problem ontology development. The problem of automated circuit partitioning problem clustering appears because of integrated data comparison. This data is represented by different dimension structures. The goal of this work is the development of circuit partitioning problem clustering method based on adjacency matrix unification. The hypergraph model of circuit representation was chosen, circuit partitioning problem was formalized. The case of adjacency matrix with different dimension clustering was observed. The novelty of proposed method is the inclusion of matrix with different dimension unification procedure in the generic clustering method.
机译:本工作涉及人工智能研究。为了适合任务类型和计算资源的目的,工程软件基准测试研究的问题在今天很重要。通常通过情报决策支持系统(IDSS)的帮助来解决此问题。领域本体是此类系统中的典型知识表示模型。手动本体开发是一个耗时且昂贵的过程。由于电路划分问题的形式化繁多,因此聚类是自动化电路划分问题本体开发的必要步骤。由于集成了数据比较,因此出现了自动电路分区问题群集的问题。此数据由不同的维度结构表示。这项工作的目的是开发基于邻接矩阵统一的电路划分问题聚类方法。选择了电路表示的超图模型,形式化了电路划分问题。观察到具有不同维聚类的邻接矩阵的情况。所提出的方法的新颖性在于在通用聚类方法中包括具有不同维统一过程的矩阵。

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