Scalable system map library for address map and data integrity verification

摘要

Address map and data integrity verification are the most important parts of SoC (System-on-Chip) verification especially at interconnect, sub-system and chip level. This paper discusses the challenges in the traditional way of address map and data integrity verification of today's SoC and describes how these challenges were addressed by a SystemVerilog based Scalable System Map library. The paper explains the facilities provided by the library for generating random stimulus, scoreboarding and a built-in functional coverage model. It also explains how the language limitations were tackled in making the library reusable within and across projects.