Early system analysis of cache performance for RISC systems

摘要

The implications of packaging and interconnection technologies forreduced instruction set computing (RISC) microprocessor memoryhierarchies are examined. Prior early analysis tools have taken eithercache performance or interconnection models into consideration. Heresuch analyses are combined and extended to be more specific to RISCmicroprocessor cache systems. The resulting first-order model allowsinteractive investigation of tradeoffs at prenetlist phases of design.After summarizing the model, several test cases are presented whichillustrate trends and begin to quantify design tradeoffs