Boundary-scan test structures and test-bench compilation in amultichip module synthesis system

摘要

The authors present a testing methodology for multichip module(MCM) designs, which were automatically generated by a behavioralsynthesis system. The testability of the design was enhanced byautomatic insertion of boundary scan architecture in every chip of theMCM design. The test vectors for the synthesized design wereautomatically derived from the behavioral test vectors, which were usedto validate the behavioral model of the design. The test vectors weretransformed into a serial format as required by the test structures andfinally represented in WAVES