A single phase parallel power processing scheme with input-shuntpower factor correction stage

摘要

A single-phase parallel power processing scheme withninput-paralleled power factor correction stage is proposed. The inputncurrent in the proposed scheme is nearly-sinusoidal with power factornclose to unity. This scheme is very attractive for systems with two ornmore independent loads, each requiring an AC-DC power converter. Annexample of one such system is a personal computer (the monitor and thenCPU units). For such a system, the proposed scheme is both costneffective and efficient than the popular two-stage cascaded scheme. Thenscheme is implemented using a half-bride boost PFC stage, and isnanalysed in detail. Analytical plots and expressions useful to a designnengineer, have been developed. Switched and averaged model simulationnresults, and experimental results are also included. An efficiency ofn93.78% at 90 V input, and a power factor of 0.999 were obtainednexperimentally. The possible circuit variations of the proposed schemenhave also been identified