Recent developments in neural network hardware implementations are examined. VLSI fabrication limitations have led to a close scrutiny of existing neural network paradigms in an attempt to develop architectures which can more easily be implemented in hardware. This feedback loop has already inspired new and promising architectures as well as a search for more universal performance measurement criteria. In the near future the most cost effective research tools will probably continue to be conventional parallel architectures. However, in the more distant future silicon implementations of architectures which mimic biological systems effectively seem inevitable.
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