Architecture and Design Methodology of 32KByte Integrated Cache Memory

摘要

The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache memory[1]. The device integrates data/instruction memory, tag memory and a comparator on a chip. It serves as a cache memory of several host MPUs by aluminum masterslice.