A simulation-based methodology for test program verification is presented. Executing test programs on a virtual test system allows simulation of Device Under Test (DUT) behavior. Simulating both device and test hardware and software allows test engineers to check and debug test programs without fabricated devices. It results in a gain of time and permits design and test to occur concurrently. This also yields better overall circuit testability. Our effort concerns development of Automatic Testing Equipment (ATE) model and software interfaces to link the simulator with both design tools and test tools. Further, we propose extending the general fault simulation concept to analog world. Fault models are suggested and tools for fault simulation automation have been developed. They include fault list generation, simulation control and result analysis as well.
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