Performance Evaluation of a Noise Canceller Filter to be used in Codesign Techniques

摘要

Codesign techniques allow exploring different design alternatives at the system level specification by means of realizations in hardware and software for each composing blocks, and thus to evaluate the system performance before choosing the final implementation. In this paper the performance estimation in terms of area, time and power dissipation of a noise canceller filter both in software and hardware implementations is presented. The approximation has consisted of the specification of the problem in ANSI C and its transformation through synthesis tools into assembler code for the DSP 56000 microprocessor and into RTL VHDL synthesizable code by means of SPARK [3]. Also more precise hardware estimation for FPGA''s and standard cells is presented.