Generation of Hardware Description Languagesfrom Modelisation tools based on Meta-modelisation

摘要

One of the main problems when creating systems lies in the different tools andrnmethods used by the various disciplines. Even when doing calculators and computers, with therninvolvement of only two disciplines, hardware and software, this situation raises many problemsrnearly in the design phase and has important consequences on the result. A way to break this wallrnwould be to standardize the efforts around a single design tool, used by the systems, software andrnhardware engineers as well. As an enabler for such a standardization capability, this paperrnpresents a generator of hardware description languages that uses a meta-model. A major benefitrnis to generate code such as VHDL, Verilog or System C from various modelling tools like UML,rnI-Logix’s Statemate or even from other sources.