An Analyzable On-Chip Network Architecture for Embedded Systems

摘要

In this paper, an on-chip network architecture designed especially for embedded systems is presented. Furthermore, a corresponding stochastic model based on discrete-time Markov chains is proposed to enable fast and cycle accurate performance evaluation of the corresponding on-chip network. The stochastic model generation is still work-in-progress. In addition, a synthesizable implementation of the network architecture will be developed in a Hardware Description Language like VHDL or SystemC. The goal of this work is to present an analytical model, a simulation, and a realizable model of an on-chip network to improve SoC design. Nevertheless, the proposed performance evaluation model of on-chip networks lacks of two important features. First, it is assumed that succeeding packets are mutually independent. No correlation between packets exists. It is not possible to emulate bursts of packets with this model. This leads to too optimistic results if the correlation of packet sequences is neglected. Extensions of the model are necessary to deal with the behavior of correlated packets. Second, systems where real-time constraints have to be met, like guaranteed throughput or a maximum delay for certain messages, cannot properly be investigated with the proposed model. The randomness that is introduced in the arbiter of the routers does not allow priorities for certain packets. Nevertheless, this problem could be overcome by separation of best-effort traffic - covered with the model in this paper- and traffic with a guaranteed service (Quality of Service) character. Separation could be realized by extending the network architecture with virtual channels: one channel for best-effort traffic and one or more for the traffic with real-time constraints.