Experience in Virtual Testing of RSD cyclic A/D converters

摘要

This paper deals with the ADC non-linearity extraction using a newly developed virtual testing environment (VTE). The VTE proposed is built on Verilog-A implementation of the servo-loop unit fully integrated into Cadence design environment. The servo-loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced servo-loop version focusing on behavioral and transistor-level example of the residual signed digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.