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Design of a dynamic frequency compensation low dropout voltage regulator with buffer impedance attenuation

机译:具有缓冲阻抗衰减的动态频率补偿低压差稳压器的设计

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This paper presents a low-drop (LDO) linear regulator with buffer impedance attenuation (BIA) for frequency compensation. This novel proposed LDO take advantage of the dynamically-biased shunt feedback in the buffer stage, which could lower its output resistance for driving the pass device to achieve fast response. Implemented in 0.35μm CMOS process, the LDO dissipates 184μA quiescent current and is able to deliver up to 100mA load current. With a 2.3μF output capacitance, the maximum transient-output variation is 25mV with full-load step change of 100mA. The proposed circuit will find application in the battery-powered portable devices.
机译:本文提出了一种具有缓冲阻抗衰减(BIA)的低压(LDO)线性稳压器,用于频率补偿。提出的这种新颖的LDO利用了缓冲级中的动态偏置并联反馈,可以降低其输出电阻,以驱动通过器件以实现快速响应。 LDO采用0.35μmCMOS工艺实现,耗散184μA静态电流,并能够提供高达100mA的负载电流。输出电容为2.3μF时,最大瞬态输出变化为25mV,满载阶跃变化为100mA。拟议的电路将在电池供电的便携式设备中找到应用。

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