Investigating architectural trade-offs in designing wide-issue instruction-level parallel processors in general, and very long instruction workd (VLIW) architectures in particular requires a powerful optimising compiler. In this paper, we describe the structure of a VLIW compiler based on hyperblock scheduling. Hyperblock is a block structure for compiler optimisations and scheduling using predicated execution. Supporting predicated execution introduces new challenges in instruction scheduling and register allocation. We describe the implementation trade-offs and how we employ the SUIF and machine SUIF compiler libraries, which are available from Stanford and Harvard universities respectively, to accelerate the implementation process.
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