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Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses

机译:具有非事务性内存访问的事务性内存的机械验证

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Transactional memory is a programming abstraction intended to simplify the synchronization of conflicting memory accesses (by concurrent threads) without the difficulties associated with locks. In a previous work we presented a formal framework for proving that a transactional memory implementation satisfies its specifications and provided with model checking verification of some using small instantiations. This paper extends the previous work to capture non-transactional accesses to memory, which occurs, for example, when using legacy code. We provide a mechanical proof of the soundness of the verification method, as well as a mechanical verification of a version of the popular TCC implementation that includes non-transactional memory accesses. The verification is performed by the deductive temporal checker tlpvs.
机译:事务性内存是一种编程抽象,旨在简化冲突内存访问(并发线程)的同步,而不会带来与锁相关的困难。在先前的工作中,我们提供了一个正式的框架来证明事务性存储器实现满足其规范,并提供了使用小实例化对某些模型进行模型检查的验证。本文扩展了先前的工作,以捕获对内存的非事务访问,例如在使用旧版代码时发生的访问。我们提供了验证方法健全性的机械证明,以及包括非事务性存储器访问在内的流行TCC实施版本的机械验证。验证由演绎时间检查器tlpvs执行。

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