An integrated 20-bit 33/5M events/s AER sensor interface with 10ns time-stamping and hardware-accelerated event pre-processing

摘要

This paper presents a custom data bridge that interfaces the continuous-time world of asynchronous address-events (AER) to the realm of conventional digital data processing. The main focus in the design of the interface was on precisely maintaining the inherent timing information of AER sensor data while providing robust peak-rate handling, DMA functionality and a novel event-rate dependent system control mechanism. The sensor interface can be integrated with standard CMOS logic in an AER processing system-on-chip and implements hardware-accelerated event pre-processing including pre-FIFO high-resolution time-stamping, address masking for ROI and event-rate dependent IRQ generation without loading a downstream processing device. The sensor interface has been implemented in a 0.18µm CMOS process and achieves peak AER event rates of 33M events/sec and sustained AER event rates of 5.125M events/sec at 10ns time-stamp resolution. We discuss design considerations and implementation details and show measurement results from the fabricated chip.