Engine for Characterization of Defects, Overlay and Critical Dimension Control for Double Exposure Processes for Advanced Logic Nodes

摘要

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11 -nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.