首页> 外文会议>Advancements in Nuclear Instrumentation Measurement Methods and their Applications (ANIMMA), 2011 2nd International Conference on >Design of a monolithic multichannel front-end readout ASIC for PET imaging based on scintillation crystals read out by photodetectors at both ends
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Design of a monolithic multichannel front-end readout ASIC for PET imaging based on scintillation crystals read out by photodetectors at both ends

机译:基于两端光电探测器读取的闪烁晶体的PET成像单片多通道前端读取ASIC的设计

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This paper presents the design techniques of a monolithic multichannel front-end readout chip integrated with both high-accuracy TDC and high-resolution ADC for the PET using LYSO(Ce) crystals read out by MCP PMT at both ends. In the front-end readout chain, a regulated cascade (RGC) preamplifier is employed in every channel for amplifying the current signals generated from MCP detector. A gain-adjustment stage, an integrator and a pulse shaper are employed for pulse height analysis which changes the width of the pulses. A discriminator is placed after the preamplifier to generate triggers. These triggers are sent to a sub-nanosecond TDC for measurement and digitizing. The peak values of the shaped pulses are digitized by a multichannel time-based ADC for measurement. Three prototype chips are designed in AMS 0.35 μm CMOS technology. In the front-end readout prototype chip, the dynamic range, the linearity, and the power dissipation are optimized. The input dynamic range from few fC to more than 100 pC can be achieved. The analog output range of the front-end readout circuits is from 1.2 V to 3.2 V. The shaping time is 280 ns and the power dissipation is reduced to less than 15 mW. In the TDC chip based on a DLL array, the RMS jitter and the peak-to-peak jitter of the used DLL are reduced to 7 ps and 21 ps, respectively. The bin size of the TDC has been reduced to 71ps with a reference clock of 100 MHz. In the multichannel time-based ADC chip, a maximum resolution of 12 bits, a sampling rate of ~1 MS/s, and the power dissipation of 3 mW ° 0.2 mW/channel are achieved.
机译:本文介绍了一种单片多通道前端读取芯片的设计技术,该芯片集成了高精度TDC和高分辨率ADC,该芯片使用两端均由MCP PMT读出的LYSO(Ce)晶体。在前端读出链中,每个通道都采用了一个可调节的级联(RGC)前置放大器,用于放大从MCP检测器产生的电流信号。增益调节级,积分器和脉冲整形器用于脉冲高度分析,从而改变脉冲的宽度。在前置放大器之后放置一个鉴别器以产生触发信号。这些触发信号发送到亚纳秒TDC进行测量和数字化。整形脉冲的峰值由基于多通道时间的ADC进行数字化以进行测量。采用AMS 0.35μmCMOS技术设计了三个原型芯片。在前端读出原型芯片中,动态范围,线性度和功耗得到了优化。可以实现从几fC到100 pC以上的输入动态范围。前端读出电路的模拟输出范围为1.2 V至3.2V。整形时间为280 ns,功耗降低至小于15 mW。在基于DLL阵列的TDC芯片中,所用DLL的RMS抖动和峰峰值抖动分别降至7 ps和21 ps。使用100 MHz的参考时钟时,TDC的bin大小已减小至71ps。在多通道基于时间的ADC芯片中,可实现12位的最大分辨率,〜1 MS / s的采样率以及3 mW±0.2 mW /通道的功耗。

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