Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis

摘要

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of bit-serial arithmetic circuits, which frequently appear in real-time DSP architectures. The potential of the proposed approach is examined through experimental synthesis of bit-serial constant-coefficient multipliers. A new version of the EGG system can generate the optimal bit-serial multipliers of 8-bit coefficients with a 100% success rate in 15 minutes on an average.