A Study of a Parallel Architecture for Accelerating Batch-Learning Self-Organizing Map by using Dedicated Hardware

摘要

Batch-learning SOM (BL-SOM) is known as one type of SOM, where all input vectors are processed in one batch and updated collectively. The advantage of BL-SOM is that the resulting map is obtained independently with the order of input vectors. However, when applied to a large set of input vectors, the amount of computation becomes enormous. In this paper, we investigate a parallel architecture for accelerating Batch-learning Self-organizing map by using dedicated hardware. In the evaluation, we present the estimation results of the relationship between the execution time and chip area for various degrees of parallelism.