Application of circuit-level hot-carrier reliability simulation tomemory design

摘要

We have applied hot-carrier circuit-level simulation to entirencircuits of a few thousand to over 12 K transistors using a simple butnaccurate degradation model for reliability verification of actual memorynproducts. Previous published applications were small scale (few tens ofntransistors or individual circuit blocks) or for experimental purposes.nBy applying simulation to entire circuits, areas with worst degradationnare not missed due to simulating only certain circuit blocks. Varyingndegradation depending upon actual products make accurate total-circuitnsimulation a crucial part of the early design process as technologynadvances into the deep sub-micron high clock rate regime