A 5.1 ns, 5000 gate, CMOS PLD with selectable frequencymultiplication and in-system programmability

摘要

A high density programmable logic device (PLD) specificallyndeveloped for high performance and for ease of use in production flowsnis presented. This device is designed on a 0.5 μm triple layer metalnprocess to produce a 55 kmil² die size and with the built-innfrequency multiplier, allows system performance of up to 140 MHz to benachieved