IO buffer for high performance, low-power application

摘要

An IO buffer architecture is shown which provides fast outputntransitions as well as efficient voltage level shifting from the chipninterior. The buffer contains a feedback circuit which damps ringingnassociated with supply bounce. Fast voltage converters are demonstratednwhich allow the core to operate at a lower voltage (1.8 V), withoutnsignificant delay penalties on the IO (at 3.6 V). These novel circuitsnare important for high performance, low power applications, such asnwireless DSPs