A 10 GHz Up-conversion Mixer with 13.6 dBm OIP3 Using Regulator-based Linearized GmStage and Harmonic Nulling

摘要

This paper presents a highly linear up-conversion mixer operating at 10 GHz. A regulator-based linearized transconductance (gm) stage is adopted for linear voltage-to-current conversion. A harmonic nulling technique is used to suppress the even harmonics of the switching pairs, thus improve their linearity performance. As the proof-of-concept, two mixers, one with the harmonic nulling technique and the other one without the harmonic nulling technique, were manufactured in IBM 32nm SOI CMOS process. The one with the harmonic nulling technique demonstrates 9.1 dB improvement in OIP3. Overall, the mixer chip achieves a state-of-the-art OIP3 of 13.6 dBm, a conversion gain (CG) of 1 dB and the difference between OIP3 and OPn1dBnof 19.8 dB (OP1ndBnis −6.2 dBm). The mixer core occupies 0.32×0.27 mmn²nchip area while consuming 15.4 mW DC power including the LO driver amplifiers.