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IIR digital filter design implemented on FPGA for myoelectric signals

机译:在FPGA上实现的用于肌电信号的IIR数字滤波器设计

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In order to attenuate the added noise by electric network used by myoelectric signals acquisition equipment, in this research work, it is developed an IIR digital filter implemented on FPGA. This filter removes a specific spectra frequencies without adding noise to the signal, which allows a better performance in the usage that is given to the signals. The filter coefficients are taken and proved from MATLAB functions. Then, those are transferred to the filter design in the FPGA. For this purpose, it was used a Basys 3 of Xilinx Artix-7 family and the design was implemented in Vivado Design Suite. The filtered signal does not present additional noise and it was eliminated the desired frequency.
机译:为了减轻肌电信号采集设备使用的电网所增加的噪声,在这项研究工作中,开发了一种在FPGA上实现的IIR数字滤波器。该滤波器在不增加信号噪声的情况下消除了特定的频谱频率,从而在提供给信号的使用中具有更好的性能。滤波器系数取自MATLAB函数并得到证明。然后,将它们传输到FPGA中的滤波器设计。为此,它使用了Xilinx Artix-7系列的Basys 3,并在Vivado Design Suite中实现了该设计。滤波后的信号不会产生额外的噪声,因此消除了所需的频率。

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