A novel modified low power pulse triggered flip-flop

摘要

This paper presents the design of a modified pulse triggered Flip-Flop (PTFF) to overcome the several shortcomings in the existing implicit (ip) and explicit (ep) type of PTFF. First, it eliminates the short circuit path which exists from VDD to GND to reduce the power consumption and clock tree power at higher switching activity. To verify the robustness of circuit proposed PTFF is analyzed at different corner cases. Again clock gating technique is applied to this modified PTFF to reduce power at low data switching activity by driving the FF into sleep mode. Simulations are carried out using 180 nm CMOS technology to validate the result.