Minterm based synthesis and optimization of asynchronous dual-rail encoded functional modules

摘要

As the feature size of semiconductor technology continues to scale down, conventional synchronous circuit design methods encounter more and more design challenges, one of which is the routing of global clock trees meeting timing and power requirements. Asynchronous circuits, which do not rely on global synchronization, provide alternative opportunities to their synchronous counterparts. This paper targets one class of asynchronous circuits with dual-rail encoded data and a high level of timing robustness. Transistor-level optimization methods are introduced to reduce the complexity of functional modules designed with traditional min-term based synthesis methods, while still preserving the timing robustness level. With the methods introduced in this paper, a wide spectrum of dual-rail encoded functional modules can be implemented in a design library for the asynchronous circuit synthesis with further area and performance optimization.