FPGA prototyping of a STAR-based time-delay estimator for 5G radio access

摘要

Code-domain non-orthogonal multiple access (NOMA), a much more sophisticated and efficient generalization of code division multiple access (CDMA), is a promising candidate for future 5G transceivers. Precisely, the CDMA Spatio-Temporal Array-Receiver (STAR) transceiver lends itself to very flexible reconfiguration and adaptation to most NOMA-type radio access technologies. It also possesses among other assets extremely high temporal synchronization capabilities. In this paper, we tackle the hardware feasibility of STAR and provide a proof of concept for a STAR-based time-delay estimator (TDE) through an FPGA-based real-time operational prototype running on a MiniBee Software-Defined-Radio (SDR) platform. We propose a modular, versatile, and reconfigurable architecture for the most basic and simplest “canonic” version of STAR at very low usage of FPGA resources, thereby paving the way for the quick implementation of extended and more complex configurations of this powerful transceiver. The real-time performances of the new prototype in terms of time-delay tracking accuracy compared to the original reference MATLAB version confirm the high precision and robustness of our new design to quantization errors and to all other hardware implementation imperfections.