Analysis and design method of ZCS DC-DC converter in consideration of the parasitic capacitance of switch and its effect on loss reduction

摘要

This paper proposes a new design method to minimize the cause of parasitic oscillation in zero-current-switching (ZCS) DC-DC converter. The parasitic capacitance in switche is considered in circuit operation, a design of the ZCS DC-DC converter is optimized by proposed design method. With some prerequisites and assumptions, the waveform equations of the parasitic oscillations are analytically derived. The equations show the essential condition to suppress the parasitic oscillations and designing procedure of the auxiliary circuit. A 90 VDC/385 VDC, 300 W, operating 200 kHz prototype has been built and evaluated. The experimental results confirmed the validity and switch loss reduction effect of the proposed design method. The main switch loss has been measured approximately 37% smaller than conventional design method.