Power optimization for video application using clock-gating technique

摘要

Image and video processing is an important topic that has risen with the digitization of visual content. One of the characteristics of video processing applications is their huge consumption of resources and power. This problem is accentuated especially for mobile devices which have a limited energy supply. In this paper, we propose a method for dynamic power minimization through clock gating technique at the block level. The proposed approach is used for an RGB to HMMD converter and implemented on Virtex-5 FPGA. The obtained results shows a power minimization over 20% with only few added resources.