Dept. of Comput. Sci. Eng., Pennsylvania State Univ., University Park, PA, USA;
cache storage; multi-threading; multiprocessing systems; LRU policy; architecture-level schemes; cycle-accurate simulation infrastructure; data locality-oriented optimizations; energy savings; last-level cache misses; manycore systems; memory controller; memory queuing latency; multithreaded applications; on-chip network; on-chip network latency optimization; victim cache line selection; Computational modeling; Context; Data models; Memory management; Multicore processing; Optimization; System-on-chip; manycore; memory;
机译:苯:多核系统的节能分布式混合缓存架构
机译:通过结合使用拆分缓存,受害者缓存和流缓冲区来提高数据缓存性能
机译:支持缓存的电源线通信网络:缓存节点选择和回程能量优化
机译:量化和优化受害者缓存行选择在多核系统中的影响
机译:使用凸优化对电力系统不确定性的影响进行量化
机译:基于粒子群算法的配电系统故障分类的支持向量机特征选择和参数优化
机译:现代内存子系统对模板计算缓存优化的影响
机译:受害者迁移:在私有和共享Cmp缓存之间动态调整