Life estimation of analog IC based on accelerated degradation testing

摘要

For high reliability semiconductor analog ICs, it is difficult to estimate their lifetime by using traditional reliability analysis methods since no enough failure data can be obtained in a relatively short period of time. Aiming at this problem, firstly, a general procedure for an accelerated degradation testing was proposed to analyze the lifetime of analog ICs under actual operating conditions according to the characteristics of their degradation behavior in this paper. Then, accelerated models and performance degradation models of analog ICs were introduced. Finally, the engineering practicability of the presented method is verified with a case of a certain type of voltage reference analog IC applied in certain aerospace electronic system.