Analysis and design of divide-by-three LC-CMOS frequency dividers

摘要

Divide-by-three frequency dividers, based on a parallel injection, are analyzed and the actual locking phenomenon underlying their operation is shown. Analytical results allow us to predict the output steady-states and the locking range in terms of the circuit parameters, thus obtaining useful design insights. The derived results are shown to be very close to SPICE simulation results for a 0.13μm RF-CMOS process.