A clock and data recovery circuit with anti-second-harmonic lock

摘要

A phase-locked-loop (PLL) based clock and data recovery (CDR) is implemented, which incorporates a full-rate mixer-type linear phase detector (PD) and a full-rate automatic frequency locked loop (FLL). And in allusion to the drawback of second harmonic lock of the realized CDR circuit, an automatic monitor circuit using two AND gates and a V-to-I converter is proposed. By driving large current source to inject a current into the loop filter in due time, the monitor circuit can not only resist second harmonic lock, but also shorten the locking time of the CDR circuit. Experimental results show 20.4 ps peak-to-peak jitter for 2¹⁵−1 pseudorandom bit sequence (PRBS) input data at a rate of 1.2 Gb/s and 97mW power at 1.8V power supply.