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A SIMD-accelerated software rendering pipeline for 3D graphics processing

机译:用于3D图形处理的SIMD加速软件渲染管道

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This paper presents a SIMD-accelerated software rendering pipeline for 3D graphics processing with multi-core architecture. The multi-core architecture is based on ARMv5 ISA which employs a SIMD unit developed by this work. We also propose a window search bounding box algorithm that can achieve zero failure in pixel tests so that speedup traversal stage is about 20 times faster than the traditional method. Finally, we use an early culling strategy to decrease unnecessary lighting operations.
机译:本文提出了一种用于多核体系结构的3D图形处理的SIMD加速软件渲染管道。多核体系结构基于ARMv5 ISA,它采用了这项工作开发的SIMD单元。我们还提出了一种窗口搜索边界框算法,该算法可以在像素测试中实现零失败,因此加速遍历阶段的速度比传统方法快20倍。最后,我们使用早期淘汰策略来减少不必要的照明操作。

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