Hardware realization of a low complexity fading filter for Multipath Rayleigh fading simulator

摘要

A low-complexity high performance Rayleigh fading simulator, and its Field Programmable Gate Array (FPGA) implementation are presented. This proposed method is a variant of the method of filtering of the white Gaussian noise where the filter design is accomplished in the analog domain and transferred into digital domain. The proposed model is compared with improved Jakes' model [1], auto-regressive filtering [2] and IDFT [3] techniques, in performance and computational complexity. Proposed method outperforms AR(20) filter and modified Jakes' generators in performance. Although IDFT method achieves the best performance, it brings a significant cost in storage and is undesirable. The proposed method achieves high performance with the lowest complexity, and its performance has been verified on Virtex4 and Spartan3e FPGA platforms. Our fixed-point Rayleigh fading-channel simulator utilizes only 2% of the configurable slices, 1% of the Look-Up-Table (LUT) resources and 3% of the dedicated multipliers on a Xilinx Virtex4 - xc4vsx35 FPGA platform.