Design and Real Time Implementation of a Radar Data Extractor

摘要

In this paper, we propose a parallel processing architecture, based on two TMS320C44 VME-bus DSP boards, for real time implementation of Cell Averaging and Clutter Map Constant False Alarm Rate (CFAR) detectors, and a data extractor based on a centroidal interpolation of the position of the detected target. The optimal processing speed has been achieved by fully exploiting the capacities of the 'C44 processor. The implemented system is well adapted for two dimension radars. The overall processing scheme interconnections and the real time implementation results are presented and discussed.