DETERMINISTIC AND STATISTICAL RELIABILITY OF SURFACE MOUNT COMPONENTS

摘要

This paper is to investigate both deterministic and statistical aspects of thermal reliability of solder joints of surface mount leadless components (SMLCs). The emphasis is on bridging deterministic with statistical reliability prediction. A reliable methodology has been established to predict the failure rate at accelerated life tests (ALTs) and field failed rate in terms of key statistical parameters of design, environmental condition, and material selection due to the uncertainty from the component manufacturing/assembly, temperature profile of ALTs and field environmental conditions, and material property. Analytical equations and solutions of inelastic strain range and fatigue life for simplified joint geometry have been developed from deterministic approach. They are furthermore utilized to obtain the failure functions of thermal fatigue caused by both crack initiation and crack propagation from multivariable distributions. First Order Reliability Model (FORM) has been extended by combining Taylor series technique with central limit theorem (CLT). An important outcome is that the statistical fatigue life is a lognormal distribution in which its parameters can be analytically evaluated by the approximate method with satisfactory accuracy for small COVs (COV=mean/deviation) of random variables (RVs). Specifically, SMLCs have been investigated on inelastic strain distribution, fatigue life distribution, failure and reliability functions, and failure rate prediction based on the statistical distributions of the solder joint height, solder paste size, temperature profile, and the experimental property of the eutectic solder alloy. Moreover, the component failure under two failure modes, i.e., both crack initiation and crack propagation, has been performed to illustrate the significance of failure criteria selection and address the data collection in field. Additionally, the simulation of realistic solder joint geometry and damage-based failure processes will be also presented. The developed methodology can be directly used for the board-level reliability prediction of advanced electronic packages such as BGAs, CSPs, QFPs, and Flip-chips.