A Prolog-Based Hardware Development Environment

摘要

This paper presents a Hardware Development Environment based on the logic programming language Prolog. Central to this environment are a hardware description notation called HIDE, and a high level generator, which takes an application specific, high level algorithm description, and translates it into a HIDE description. The latter describes scaleable and parameterised architectures using a small set of Prolog constructors. EDIF netlists can be automatically generated from HIDE descriptions. The high-level algorithm descriptions are based on a library of reusable Hardware Skeletons. A hardware skeleton is a parameterised description of a task-specific architecture, to which the user can supply parameters such as values, functions or even other skeletons. A skeleton contains built-in rules, written in Prolog that will apply optimisations specific to the target hardware at the implementation phase. This is the key towards the satisfaction of the dual requirement of high-level abstract hardware design and hardware efficiency.