A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA

摘要

To achieve area-efficiency and high SNR, a novel digital front-end of a 16-bit audio DAC including a 4-stage interpolator and a 3^rd-order delta-sigma (ΣΔ) modulator is proposed. An improved common subexpression elimination (CSE) method is used for implementing the interpolator to save the hardware overhead. And a novel data weighted averaging (DWA) technique named as dual cycle shifted DWA is applied to the 4-bit ΣΔ modulator to reduce the mismatch errors without introducing signal-dependent tones. Implemented in a standard 0.18-µm 1P6M LOGIC salicide process, the proposed design achieves a peak SNR of 103.9-dB and a DR of 104.3-dB, which proves that the proposed work achieves the design goal well.