Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays

摘要

A novel methodology for designing interconnection architectures, targeting to general-purpose FPGAs, is introduced. The design parameters for this architecture are extracted after the implementation and profiling numerous applications on Virtex FPGAs. Among the design parameters, we study the connectivity demand for each (x, y) point of the interconnection network. The derived data are appropriately manipulated to build a topology consisting of different Switch Boxes (SB), which are assigned over the FPGA architecture taking into account the connectivity requirements for each part of the device. The selected architecture resulted from the specific Pareto optimal points which tradeoffs the maximum operation frequency versus the energy consumption. The methodology is software supported by three new CAD tools, part of the MEANDER Framework. Using numerous applications, extensive comparison study in terms of several design parameters proves the efficiency of the proposed interconnection compared to Virtex-style FPGAs. More specifically, we achieve an average increase in operation frequency by 31%, a reduction in leakage power and energy consumption by 8% and 22%, respectively.