Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

摘要

In this paper, we present a new inverter topology decreasing the process variability influence on performances of a ring oscillator. Using FDSOI technology, we propose a new complementary structure based on a pair of Back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals. The complementary outputs of the inverters are crossing at V_(DD) divided by 2. Monte Carlo (MC) simulations exhibit a mean value of V_(DD)/2 = 500 mV, and the standard deviation is about σ = 2.7 mV. Moreover, this topology enables a VCRO with an even number of inverters. This latter feature makes it easy to perform quadrature VCOs (QVCO), which are used in RF receiver architectures for image frequency rejection. We have verified this characteristic by estimating the phase between two outputs using Monte Carlo simulations. The mean value of the phase is 45° (for a 4 complementary inverters ring oscillator) and the standard deviation is σ = 0.13°. Finally, we have studied the jitter of such oscillator and proposed some explanations.