A low-power 3.25GS/s 4^th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing

摘要

Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIR-based beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance was not shown.