Clock synchronization scheme for fractional multiplication systems

摘要

A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.