CLOCK SYNCHRONIZATION SCHEME FOR FRACTIONAL MULTIPLICATION SYSTEMS

摘要

A circuit for synchronizing a multiplied system clocksignal includes a device for generating a system clock signal(10, 34), a first device (30) that receives the system clocksignal and generates a synchronization signal (20) and atleast one second device (31, 32) that receives the systemclock signal and the synchronization signal. Each of thesecond devices includes a device (40, 71, 74, 81, 84) formultiplying the system clock signal to produce the multipliedsystem clock signal and a device for synchronizing themultiplied system clock signal with each other multipliedsystem clock signal produced by the other second devicesbased on the synchronization signal.