CLOCK SYNCHRONIZATION SCHEME FOR FRACTIONAL MULTIPLICATION SYSTEMS

摘要

Circuitry for synchronizing multiple system clock signals includes an apparatus for generating a system clock signal, a first apparatus for receiving the system clock signal and generating a synchronization signal, and one or more receiving the system clock signal and the synchronization signal. And a second device. Each of the second devices may comprise a device for multiplying the system clock signal to produce a multi-system clock signal and another multi-system clock signal produced by another second device based on the synchronization signal. And a device for synchronizing.