首页> 外国专利> Method of fabricating CMOS thin film transistor (TFT) and CMOS TFT fabricated using the same

Method of fabricating CMOS thin film transistor (TFT) and CMOS TFT fabricated using the same

机译:CMOS薄膜晶体管的制造方法以及使用该薄膜晶体管制造的CMOS TFT

摘要

A method of fabricating a CMOS thin film transistor (TFT) and a CMOS TFT fabricated using the method involve provision of a substrate having a first region and a second region. A first semiconductor layer and a second semiconductor layer are formed on the first and second regions, respectively. A gate insulating layer having a first portion overlying end portions of the first semiconductor layer, and a second portion overlying end portions of the second semiconductor layer and having a thickness larger than that of the first portion, is formed on the semiconductor layers. An ion doping mask pattern is formed on the gate insulating layer. First impurities are doped in end portions of the first semiconductor layer using the ion doping mask pattern as a mask, and second impurities having a conductivity type different from that of the first impurities are doped in end portions of the second semiconductor layer. As a result, it is possible to reduce the number of masks, and to simplify the processes required for manufacture of the CMOS TFT.
机译:制造CMOS薄膜晶体管(TFT)的方法和使用该方法制造的CMOS TFT涉及提供具有第一区域和第二区域的基板。在第一区域和第二区域上分别形成第一半导体层和第二半导体层。在半导体层上形成栅极绝缘层,该栅极绝缘层具有覆盖第一半导体层的第一部分的第一部分和覆盖第二半导体层的第二部分的第二部分,并且厚度大于第一部分的厚度。离子掺杂掩模图案形成在栅极绝缘层上。使用离子掺杂掩模图案作为掩模在第一半导体层的端部中掺杂第一杂质,并且在第二半导体层的端部中掺杂具有与第一杂质的导电类型不同的导电类型的第二杂质。结果,可以减少掩模的数量,并且可以简化制造CMOS TFT所需的工艺。

著录项

  • 公开/公告号US7572690B2

    专利类型

  • 公开/公告日2009-08-11

    原文格式PDF

  • 申请/专利权人 EUI-HOON HWANG;

    申请/专利号US20050155781

  • 发明设计人 EUI-HOON HWANG;

    申请日2005-06-20

  • 分类号H01L29/72;

  • 国家 US

  • 入库时间 2022-08-21 19:33:35

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