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首页> 外文期刊>Journal of Low Power Electronics >A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle
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A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle

机译:一种新型坐标旋转数字计算机方法,用于节省三角函数空间局部原理

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摘要

In this work, we propose an approximate and energy-efficient CORDIC method, based on a trigonometric function spatial locality principle derived from benchmarks profiling. Successive sine/cosine computation requests cover more than 50% when the absolute phase difference is at most tendegrees. Consequently, this property suggests an optimized circuit implementation, both iterative or a succession of microrotation modules, where the last CORDIC requires fewer iterations, reducing the latency and the total energy budget at the same precision of two separate and independentinstances. Thus, this simple design strategy allows significant area and energy dissipation in general-purpose VLSI architectures, but it introduces also dramatically optimizations in applicationspecific embedded systems used in the area of signal processing and radio frequency communication.In this contribution, we introduce a method, the hardware overhead and the energy budget per single cycle. Simulation results show the total energy saving in considered benchmarks is 40% in pipelined and iterative general purposes CORDIC. Furthermore, our application-specific systems (fastFourier transform and digital oscillators for radiofrequency down conversions) show remarkable cycle savings when the successive sine/cosine computation requests are more than 70%. Finally, in this work, we extend the proposed approach to whichever phase difference less than 26.56° , asa variable for the second CORDIC number of angle rotations.
机译:在这项工作中,我们提出了一种近似和节能的CORDIC方法,基于从基准分析的基准分析中的三角函数空间位置原理。当绝对相位差处于大多数肌腱时,连续的正弦/余弦计算请求覆盖超过50%。因此,该属性表明了优化的电路实现,迭代或连续的微观调节模块,其中最后一个CORDIC需要较少的迭代,降低两个单独和独立的相同精度的延迟和总能量预算。因此,这种简单的设计策略允许通用VLSI架构中的显着区域和能量耗散,但它在信号处理和射频通信领域中使用的应用特异性嵌入式系统中引入了显着优化。在这种贡献中,我们介绍了一种方法,硬件开销和每循环的能源预算。仿真结果表明,在流水线和迭代通用目的中考虑基准的总节能40%。此外,我们的特定于应用程序的系统(FastFourier转换和用于辐射级转换的数字振荡器)在连续的正弦/余弦计算请求超过70%时节省了显着的循环节省。最后,在这项工作中,我们将所提出的方法扩展到较小的相位差小于26.56°,ASA变量对于第二码角旋转。

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